1. Field of the Invention
The present invention relates to a semiconductor IC (integrated circuit), and in particular to a high-speed semiconductor IC which consumes relatively little power, the semiconductor IC being composed essentially of micro devices.
2. Description of the Related Art
The entire disclosure of U.S. patent application Ser. No. 08/862,017 filed May 22, 1997 is expressly incorporated by reference herein.
In the field of DRAMs (dynamic random access memories) and other LSI (large scale integration) circuits, there has recently been an increased demand for decreased power consumption, increased integration density, and facilitation of battery operation. These demands have led to demands for circuits which are capable of operating at a low voltage. Vigorous development activities have been made to achieve such goals.
In order for an LSI to operate at a low voltage, it is important to reduce the threshold voltage of MOS transistors, which are important constituent elements of the LSI. However, the problem of a leak current, which occurs when a transistor is turned off, imposes a practical limit to the extent of reduction in the threshold voltage of a MOS transistor. It is also known that decreasing the supply voltage without decreasing the threshold voltage of the MOS transistor results in a noticeable deterioration of the operation speed. Various inventions have been made to solve this problem, e.g,. a technique proposed in Japanese Laid-Open Patent Publication No.6-208790 (D. TAKASHIMA).
Japanese Laid-Open Patent Publication No.6-208790 describes in its FIG. 4(b) a circuit in which a plurality of NMOS transistors are coupled in series between a NAND circuit and a power source in such a manner that the NMOS transistor located closest to the power source has a threshold voltage higher than those of all the other NMOS transistors. As a result, the NMOS transistor located closest to the power source (having a threshold voltage higher than those of the other NMOS transistors) is cut off during a stand-by state. Thus, the circuit is capable of operating rapidly at a low voltage without increasing the leak current.
However, the circuit described in Japanese Laid-Open Patent Publication No.6-208790 is not capable of operating rapidly at a low voltage when (1) the input to the circuit shifts so as to activate the high-threshold NMOS transistor, or (2) the input to the high-threshold NMOS transistor varies the latest among the inputs to all the NMOS transistors.